1. Field of the Invention
The present invention relates to the field of processing multiple pattern layers.
2. Discussion of Related Art
It is well known in the art to process semiconductor wafers by building multiple layers of conductive patterns of circuitry upon one another. As a simple example, a typical process of building a two layer semiconductor structure would be to first form a deep trench pattern via a lithographic process. This is accomplished by first adding layers of semiconductor materials, such as silicon dioxide or silicon nitride, to a flat film wafer in a well known manner such as film deposition or growth. After the layers are formed, a so-called deep trench lithographic process is performed. The deep trench lithographic process involves applying a photoresist layer onto the semiconductor layer. The photoresist layer is then exposed to light or radiation. The light or radiation passes through a patterned reticle and has a particular wavelength so as to react with the photoresist layer. The reticle defines a desired deep trench circuit pattern so that the light or radiation exposes the first layer in a pattern similar to the desired deep trench circuit pattern. Note that in the past, it was only during the process of exposing a wafer at any given stage where steps to overcome registration errors of pattern product layers were considered. After the photoresist has been exposed, chemicals are applied to the resist so that the desired deep trench circuit pattern is revealed.
After the deep trench circuit is formed in the first layer and passes inspection for defects, an etching process is performed on the layer. The etching process involves placing the wafer on a support, such as an electrostatic chuck, positioned within an ionized gas generator, such as a plasma etch chamber. Next, the plasma etch chamber is turned on so as to generate a plasma from a gas, such as HBr. The resist pattern is then transferred to the wafer in a parallel two-fold manner: 1) the plasma gases chemically interact with the exposed substrate materials of the deep trench pattern and 2) charged ions formed in the plasma are directed onto the layer so as to physically remove material from the layer.
After subsequent processing, the substrates are then returned to the lithography area to produce the next patterned layer. An active area circuit pattern is formed via a second lithographic process and a second etching process similar to the lithographic and etching processes described above. In the second so-called active area lithographic process a photoresist layer is applied as the second semiconductor pattern. The photoresist layer is exposed to light or radiation that passes through a reticle that has a pattern for forming a desired active area pattern on the second semiconductor layer. The light or radiation exposes the second layer in a pattern similar to the desired active area circuit pattern. After the photoresist has been exposed, chemicals are applied to the resist so that the desired active area circuit pattern is revealed.
Next, the wafer is placed in a second ionizing gas generator, such as a second plasma etch chamber, where the second layer undergoes an active area etch process. In this etch process, the wafer is placed within the second plasma etch chamber that processes the top layers. The active area circuit pattern is etched by the second plasma etch chamber in a manner similar to the etch process performed on the first layer. The second layer is cleaned and inspected in a manner similar to that done for the first layer.
Note that the above process continues until all layers are formed. Furthermore, the lithographic and etch processes may need to be altered from layer to layer in order to form the desired pattern in the substrate. Such altering can include using variations in plasma etch chamber design or process that is different than that used for the other layer.
FIG. 1 shows two layers formed by processes similar to those described above. As shown in FIG. 1, the active area circuits 100 have end portions 102, 104 that preferably extend in the Y-direction so that they overlap corresponding trench circuits 106, 108, respectively. The end portions 102, 104 are also preferably positioned so as to be centered on the corresponding trench circuits 106, 108. Should the end portions 102, 104 not be aligned with the centers of the corresponding circuits 106, 108, the semiconductor structure may result in unacceptable electrical performance.
Applicants have found that such misalignment can occur when one type of machine or etch chamber design and/or etching process is used during the etching step performed on the first layer while a second and different type of machine or etch chamber design and/or etching process is used during the etching step performed on the second layer. Without being confined to any one particular theory, it is believed that such misalignment can occur due to the machines/chambers used in the two etch process have differing cathode/anode ratios and/or structural geometries from one another. Such differences result in electric forces varying in both magnitude and direction near the surface of a wafer in one machine as compared to the distribution of electric forces near the wafer surface in the other machine. These differences are characterized and henceforth referred unto in terms of electric fields represented by electric field lines and in terms of derived equipotential/isopotential surfaces represented by isopotential lines. The differing of the shapes of the electric field lines/electrical isopotential surfaces results in different trajectories of ions impinging at the wafer surface for the two machines/chambers for a particular area of the wafer. The different trajectories cause a shift in the circuitry formed between subsequent layers of the wafer.
Note that there are other possible factors that can contribute to misalignment. For example, misalignment can be caused by differing electrostatic chuck designs, process parameters and/or process kits used in the two machines/chambers. In addition, the electric potential/electric fields/electric forces formed by a plasma can be thought of as having a global component due to the shape of the sheath and presheath of the plasma and a local component that depends on the shape of the electrical isopotential surfaces in the immediate neighborhood of the wafer edge. Thus, any factors that lead to differences in the sheaths and/or the presheaths of the two plasmas formed in the two chambers can lead to misalignment as well. In the case of the global component changes between the plasmas used, the plasma etch chamber geometries and/or focus ring geometries can lead to differences in the shape of the electrical isopotential surfaces. Regarding the local component associated with the shapes of the electrical isopotential surfaces near the edge of the wafer, different independent electric potential sources and differences in the edges can also lead to changes in the shapes of the electrical isopotential surface surfaces. Thus, in the case where both machines/chambers are similar structurally, misalignment can result when one or more parameters for the two etching processes differ from each other.
A schematic example of a plasma etch chamber 200 having a chamber 201 with a wall 203 is shown in FIG. 2. FIG. 2 illustrates principles that are common to differing plasma etch chambers used to etch consecutive layers of the wafer. In such plasma etch chambers, the ionized gas 202 encounters forces represented by the electric field lines 204 which are oriented perpendicular to the electrical isopotential lines 206. The ionized gas 202 is then steered via electric forces in the direction of the electric field lines 204 onto the wafer 208 that is held in place by an electrostatic chuck 210.
It is believed that the total electrical potential differences and thus the total electric field encountered by the ions at any point within the chamber can be thought of as the sum of two components: a global electrical force and a local electrical force as mentioned previously. As shown in FIG. 2, the tilt angle of the trajectory of the ions striking the top layer of wafer 208 with respect to the vertical varies with the distance from the side edge in a nonuniform manner, especially near the edge of the wafer, due to the combined effect of the global and local potentials. This nonuniform tilting results in the nonuniform etching pattern shown at the bottom of FIG. 2.
FIG. 2 represents general principles of either the first or second plasma etch chamber. As shown in FIG. 2, the electric field 204 is fairly uniform or linearly varies as viewed from the center axis 212 of the wafer and extending radially outward to a radial distance d from the center axis 212. The area of the wafer extending from center axis 212 to a radius d shall be deemed as the “central area 214.” Within the central area 214, the tilt angle of the trajectory is small and is either constant or becomes larger away from a point near the center axis 212 in an approximately linear manner. The variation of the tilt angle results in a pattern shift δ(r) of the etched pattern relative to an ideal position of the etched pattern for the particular etch chamber. Like the tilt angle, the pattern shift δ(r) is either constant or becomes larger away from a point near the center axis 212 in an approximately linear manner.
As mentioned previously, the tilt angle of the trajectory at any point of the wafer within the center area 214 will probably vary between two consecutive layers that are etched by two differing machines/processes as shown in FIG. 3. Since the tilt angle of the ion trajectory varies this means that the shapes of the electrical isopotential surfaces and electric field strength and distribution at any point across the chamber for a given layer differ from the shapes of the electrical isopotential surfaces and electric field strength and distribution at any given point across the chamber for another layer. One consequence of such a difference between the shapes of the electrical isopotential surfaces and electric field lines in consecutive layers in the central area 214 is that the circuitry formed in the consecutive layers are shifted relative to one another. This is shown in FIG. 4 where the end portions 102, 104 of each of the active area circuits 100 within the central area 214 for one layer are shifted uniformly from the corresponding centers of the deep trench circuits 106, 108 formed in an adjacent overlying layer by an imaging shift factor Δ(r) that is the result of the difference of the two pattern shifts δ(r) associated with the two etching machines/processes used. The imaging shift factor is either a constant within central area 214 or is approximately a linear function that varies depending on the x and y coordinates within the central area 214. In addition, the imaging shift factor Δ(r) is nearly radially symmetrical about the center axis 212.
As shown in FIG. 2, outside the central area 214 the shapes of the electrical isopotential surfaces and electric field lines at the peripheral area 216 of the wafer are not uniform and cannot be described as a linear phenomenon. As shown in FIG. 2, the tilt angle of the trajectory of the ions of the ionized gas initially increases moving away from the central axis 212 and then decreases going further away from the central axis 212. FIGS. 4-7 show the shift of the end portions 102, 104 with respect to the corresponding centers of the deep trench circuits 106, 108 with the peripheral area 216.
As mentioned previously, the above described uniform shifting is the result of using different plasma etch chambers and/or processes during the etching of consecutive layers of the wafer. When two identical plasma etch chambers and etch processes are used on consecutive layers of the wafer, then the ions of the ionized gas are directed equally or in the same manner onto each layer and so no net misalignment between the adjacent overlying layers occurs. Unfortunately, it is often necessary to use different plasma etch chambers and/or etching processes for different layers being formed. Thus, misalignment can occur between adjacent layers.
It is therefore an object of the present invention to correct the alignment between the circuitry of consecutive layers of a semiconductor structure.
Other objects of the present invention include improving device performance and device yields.